PSAS/ avionics/ capstone2010/ design/ tqm5200

TQM5200 Module

The TQM5200 has the Freescale PowerPC Processor MPC5200 up to 400MHz with MPC603e Processor Core which includes the following features:

This Module is supplied with 3.3V power supply.

TQM5200 Connector:

System Components

CPU Main

SDRAM / DDR Memory Interface

External Bus Interface

Peripheral Component Interconnect (PCI) Controller

ATA Controller

6 Programmable Serial Controllers (PSC)

Fast Ethernet Controller (FEC)

Universal Serial Bus Controller (USB)

Two Inter-Integrated Circuit Interfaces (I2C)

Dual CAN 2.0 A/B Controller (MSCAN)

Ethernet

The Ethernet pins are connected to two 10 pin 2mm Single row connectors. The Ethernet daughter board is attached to this connector to use the Ethernet function.

Connector Part Number : (In Stock with PSAS)

Note - Pin 7 of J1007 is connected to PO_RESET

Ethernet Pin Descriptions and Function

Pin Function Description Dir.
ETH_0 ETH_TX_EN Ethernet Transmit Enable I/O
ETH_1 ETH_TXD_0 Ethernet Transmit Data Output I/O
ETH_2 GPIO Simple General Purpose Output I/O
ETH_3 GPIO Simple General Purpose Output I/O
ETH_4 GPIO Simple General Purpose Output I/O
ETH_5 GPIO Simple General Purpose Output I/O
ETH_6 GPIO Simple General Purpose Output I/O
ETH_7 GPIO Simple General Purpose Output I/O
ETH_8 ETH_CD Ethernet Carrier Detect I/O
ETH_9 ETH_RXCLK Ethernet Receive Clock I/O
ETH_10 ETH_COL Ethernet Collision Detect Input I/O
ETH_11 ETH_TXCLK Ethernet Transmit Clock Input I/O
ETH_12 ETH_RXD0 Ethernet Receive Data Input I
ETH_13 INTERRUPT INTERRUPT I/O
ETH_14 INTERRUPT INTERRUPT I/O
ETH_15 INTERRUPT INTERRUPT I/O
ETH_16 INTERRUPT INTERRUPT I/O
ETH_17 GPIO Simple General Purpose Output with WAKE UP I/O

ATA

The Advanced Technology Attachment (ATA) Controller provides full functional compatibility with ATA-4 documentation, supporting Ultra-33. For more ATA Standards information, refer to "American National Standard for Information Technology—AT Attachment with Packet Interface Extension (ATA/ATAPI-4)".

The ATA is connected to Integrated Drive Electronic (IDE) Connector (DOM EDC4000 IDE 44Pin Horizontal Type A)

ATA Functions, Local Plus Address/Data Bus signals

PIN ATA Function Description
EXT_AD_31 n/a n/a
EXT_AD_30 n/a n/a
EXT_AD_29 n/a n/a
EXT_AD_28 n/a n/a
EXT_AD_27 n/a n/a
EXT_AD_26 n/a n/a
EXT_AD_25 n/a n/a
EXT_AD_24 n/a n/a
EXT_AD_23 n/a n/a
EXT_AD_22 n/a n/a
EXT_AD_21 n/a n/a
EXT_AD_20 n/a n/a
EXT_AD_19 n/a n/a
EXT_AD_18 ATA_SA_2 ATA Address Bit 2
EXT_AD_17 ATA_SA_1 ATA Address Bit 1
EXT_AD_16 ATA_SA_0 ATA Address Bit 0
EXT_AD_15 ATA_DATA_15 ATA Data Bit 15
EXT_AD_14 ATA_DATA_14 ATA Data Bit 14
EXT_AD_13 ATA_DATA_13 ATA Data Bit 13
EXT_AD_12 ATA_DATA_12 ATA Data Bit 12
EXT_AD_11 ATA_DATA_11 ATA Data Bit 11
EXT_AD_10 ATA_DATA_10 ATA Data Bit 10
EXT_AD_9 ATA_DATA_9 ATA Data Bit 9
EXT_AD_8 ATA_DATA_8 ATA Data Bit 8
EXT_AD_7 ATA_DATA_7 ATA Data Bit 7
EXT_AD_6 ATA_DATA_6 ATA Data Bit 6
EXT_AD_5 ATA_DATA_5 ATA Data Bit 5
EXT_AD_4 ATA_DATA_4 ATA Data Bit 4
EXT_AD_3 ATA_DATA_3 ATA Data Bit 3
EXT_AD_2 ATA_DATA_2 ATA Data Bit 2
EXT_AD_1 ATA_DATA_1 ATA Data Bit 1
EXT_AD_0 ATA_DATA_0 ATA Data Bit 0

ATA Dedicated Signals

Signal descriptions

LPCS4 and LPCS5 - (Chip select, ATA_CS (1:0))

These are the chip select signals from the host used to select the Command Block registers (see 7.2). When DMACK- is asserted, CS0- and CS1- shall be negated and transfers shall be 16-bits wide.

ATA_SA (2:0) (Device address)

This is the 3-bit binary coded address asserted by the host to access a register or data port in the device.

ATA_DATA (15:0) (Device data)

This is an 16-bit bi-directional data interface between the host and the device. The lower 8 bits are used for 8-bit register transfers. Data transfers are 16-bits wide.

ATA_IOR (Device I/O read: Ultra DMA ready: Ultra DMA data strobe)

ATA_IOR- is the strobe signal asserted by the host to read device registers or the data port.

ATA_IOW (Device I/O write: Stop Ultra DMA burst)

ATA_IOW- is the strobe signal asserted by the host to write device registers or the data port

ATA_DACK- (DMA acknowledge)

This signal shall be used by the host in response to ATA_DARQ to initiate DMA transfers.

ATA_DARQ (DMA request)

This signal, used for DMA data transfers between host and device, shall be asserted by the device when it is ready to transfer data to or from the host. For Multiword DMA transfers, the direction of data transfer is controlled by DIOR- and DIOW-. This signal is used in a handshake manner with DMACK-, i.e., the device shall wait until the host asserts DMACK- before negating DMARQ, and re-asserting DMARQ if there is more data to transfer. When a DMA operation is enabled, CS0- and CS1- shall not be asserted and transfers shall be 16-bits wide.

ATA_INTRQ (Device interrupt)

This signal is used by the selected device to interrupt the host system. When the nIEN bit is cleared to zero, and the device is selected, INTRQ shall be enabled through a tri-state buffer and shall be driven either asserted or negated.

When asserted, this signal shall be negated by the device within 400 ns of the negation of DIOR- that reads the Status register. When asserted, this signal shall be negated by the device within 400 ns of the negation of DIOW- that writes the Command register.

When the device is selected by writing to the Device/Head register while an interrupt is pending, INTRQ shall be asserted within 400 ns of the negation of ATA_IOW- that writes the Device/Head register. When the device is deselected by writing to the Device/Head register while an interrupt is pending, INTRQ shall be negated within 400 ns of the negation of DIOW- that writes the Device/Head register.

ATA_IOCHRDY:

This signal is negated to extend the host transfer cycle of any host register access (Read or Write) when the device is not ready to respond to a data transfer request. If the device requires to extend the host transfer cycle time at PIO modes 3 and above, the device shall utilize IORDY. Hosts that use PIO modes 3 and above shall support IORDY.

ATA Pin Description

PIN Function Reset Value Description
Pin ATA_DRQ
ATA ATA_DRQ logic 0 ATA DMA Request
Pin ATA_DACK
ATA ATA_DACK logic 1 ATA DMA Request
Pin ATA_IOR
ATA ATA_IOR logic 1 ATA read - 0, no read - 1
Pin ATA_IOW
ATA ATA_IOW logic 1 ATA write - 0, no write - 1
Pin ATA_IOCHDRY
ATA ATA_IOCHDRY logic 1 ATA negated to extend transfer
Pin ATA_INTRQ
ATA ATA_INTRQ logic 1 ATA Interrupt Request
Pin ATA_ISOLATION
ATA ATA_ISOLATION logic 1 ATA Levelshifter control signal

Programmable Serial Controllers 2 (PSC2)

The Controller Area Network (CAN) transceiver is connected to the PSC2

Pin Name Dir. CAN Function Description
PSC2_0 I/O CAN1_TX CAN1_TX CAN Transmit
PSC2_1 I/O CAN1_RX CAN1_RX CAN Receive
PSC2_2 I/O CAN2_TX CAN2_TX CAN Transmit
PSC2_3 I/O CAN2_RX CAN2_RX CAN Receive Data
PSC2_4 I/O GPIOw/ WAKEUP Simple General Purpose I/O with WAKE UP

Universal Serial Bus Controller-1 (USB1)

The USB1 pins are connected to the USB transceiver

Pin Name Dir. USB Description
USB_0 I/O USB1_OE USB Output Enable
USB_1 I/O USB1_TXN USB Transmit Negative
USB_2 I/O USB1_TXP USB Transmit Positive
USB_3 I USB1_RXD USB Receive Data
USB_4 I USB1_RXP USB Receive Positive
USB_5 I USB1_RXN USB Receive Positive
USB_6 I/O USB1_PORTPWR USB Port Power
USB_7 I/O USB1_SPEED USB Speed
USB_8 I/O USB1_SUSPEND USB Susupend
USB_9 I/O USB1_OVERCNT USB Over Current

Programmable Serial Controllers 3 (PSC3)

The second Universal Serial Bus Controller (USB2) transceiver is connected to the PSC3 pins.

Pin Name Dir. USB Function Description
PSC3_0 I/O USB1_OE USB Output Enable
PSC3_1 I/O USB1_TXN USB Transmit Negative
PSC3_2 I/O USB1_TXP USB Transmit Positive
PSC3_3 I USB1_RXD USB Receive Data
PSC3_4 I USB1_RXP USB Receive Positive
PSC3_5 I USB1_RXN USB Receive Positive
PSC3_6 I/O USB1_PORTPWR USB Port Power
PSC3_7 I/O USB1_SPEED USB Speed
PSC3_8 I/O USB1_SUSPEND USB Susupend
PSC3_9 I/O USB1_OVERCNT USB Over Current

JTAG (Joint Test Action Group)

The MPC5200 provides the user an IEEE 1149.1 JTAG interface to facilitate board/system testing. It also provides a Common On-Chip Processor (COP) Interface, which shares the IEEE 1149.1 JTAG port. The COP Interface provides access to the MPC5200's imbedded Freescale MPC603e G2_LE processor. This interface provides a means for executing test routines and for performing software development & debug functions.

The JTAG pins and the Reset pins are connected to a 16 pin 2mm Dual row Connector.

JTAG Pins

PIN Description
JTAG_TDO JTAG Test Data Out
JTAG_TMS JTAG Test Mode Select
JTAG_TDI JTAG Test Data In
JCPUJTAGTRST JTAG Reset
TEST_SEL_0 Scan Enable (for production test), PLLBYPASS -input, CKSTOP - output
TEST_SEL_1 ENID Input in Test Mode (for production test)
JTAG_TCK JTAG Test Clock
TEST_MODE_0 Test Mode Select 0 (for production test)
TEST_MODE_1 Test Mode Select 1 (for production test)

Reset Pins

PIN Description
!HRESET Hard Reset
!SRESET Soft Reset
!PO_RESET Power On Reset
!RESIN Reset

JTAG/Reset Connector Pin Configuration

Connector Part Number : 87758-1616

Pin Function
1 3.3V
2 JTAG_TDO
3 JTAG_TMS
4 JTAG_TDI
5 JCPUJTAGTRST
6 TEST_SEL_0
7 TEST_SEL_1
8 JTAG_TCK
9 TEST_MODE_0
10 TEST_MODE_1
11 !HRESET
12 !SRESET
13 !PO_RESET
14 !RESIN
15 GND
16 GND

General Purpose LEDs

The LED configuration were designed as per the STK5200 schematic (page 6). Connected to GPIO (General Purpose Input/Output) ports of connector X2.

LED GPIO Port
LED1003 GPIO24
LED1004 GPIO25
LED1005 GPIO26
LED1006 GPIO27
LED1007 GPIO48
LED1008 GPIO49
LED1009 GPIO50
LED1010 GPIO51

U1012

R1029, R1030, R1031, R1032, R1033, R1034, R1035, R1036

LED 1003, 1004, 1005, 1006, 1007, 1008, 1009, 1010

RGB LED

The RGB LED is connected to GPIO28, GPIO46, GPIO47.

Q1003, Q1004, Q1005

LED1002

R1037, R1038, R1039

Reference