Reset Circuitry
- Objectives:
- Verify RESET/ signal is asserted upon power up.
- Verify RESET/ is released tRPU after Vdd exceeds Vtrip (Fig. MCP130-1.1)
- Verify RESET/ remains non-asserted while APS maintains load regulation within spec (Fig. MCP130-2.2) Components needed to be installed:
- Entire SPS subsystem
- U283
Crystal Oscillator
- Objectives:
- Verify crystal oscillator always starts
- Verify crystal circuit oscillates at the correct frequency
- Observe variation in frequency (drift)
- Verify oscillator signal has an acceptable wave shape
- Verify oscillator is being divided down to the correct frequency for SPS-Sync Components needed to be installed:
- Entire SPS subsystem
- U280 ARM chip
- X281 12.0 MHz crystal
- U281 7 stage divider
USB interface
- Objectives:
- Verify endpoint enumerates
- Verify data is transmitted without error Components needed to be installed:
- Essentially everything on the schematic
ARM + Glue "power up"
- Power up sequence:
- t0 - DC applied
- t1 - MAX5902 release soft start
- t2 - C201 charges up
- t3 - LT1767 starts operating
- t4 - 2.6 V on output of SPS
- t5 - LPC2148 Oscillator starts
- t6 - 3.0 V on output of SPS
- t7 - CD4024 provides SPS Sync
- t8 - MCP130 releases CPU reset
- t9 - First instruction executed
- t10 - PLL registers programmed and 48 MHz USB clock available Key timing issues:
|
Interval |
Description |
Details |
|
t4..t5 |
Determined by LPC2148 |
When Vdd goes below 2.9 V, the LPC2148 issues a brown-out interrupt. When Vdd is below 2.6 V, the LPC2148 internally asserts it's reset. See page 42 |
|
t6..t8 |
Determined by MCP130 and is called Trpu |
Typical time is 275 ms. See MCP130 Fig. 2.3. The LPC2148 requires 10 ms; see page 38 of users manual. |
|
t3..t7 |
The SPS oscillator is free-running |
SPS_Sync has not yet been provided. The SPS should be running around 1.25 MHz. |
ARM + Glue final block testing
- Verify consistent start up
- Verify crystal response to vibration