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ARM 7 microcontroller (U280)

Part Description:

• LPC2148FBD64-S ARM-7/TDMI 16-32 bit microcontroller, 64 pin LQFP package.

Purpose:

• This is the computational resource on the node board, and facilitates communications between application specific sub systems on the node, and the avionics communications bus using the USB.

Specifications/ Calculations:

• The detail of specifying this component is provided on the [CapstoneLV2bProjectReport/Microcontroller] page.
• User manual of the Philips LPC2148 is at: http://www.semiconductors.philips.com/acrobat/usermanuals/UM10139_1.pdf
• Brief datasheet is at: http://www.semiconductors.philips.com/acrobat_download/datasheets/LPC2141_42_44_46_48_1.pdf

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Power decoupling (C285, 286, 287, 288, 291, 292, 293, 294)

C285, C286, C287, C288, C291, C292, C293, C294

Part Description:

• 10 nF, 50 volt, Chip X7R, 0805 package, Panasonic ECJ-2VB1H103K, (Digikey P/N PCC103BNCT-ND) http://www.panasonic.com/industrial/components/pdf/abj0000ce1.pdf

Purpose:

• Local transient suppression at chip. Prevents chip switching transient from going onto power rail. Also a source of very short duration energy to supply the switching transient locally.

Specifications/ Calculations:

• Typical logic guidelines use 10 to 100 nF.

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USB filtering block

• The USB bus is a potential source of harmful external noize that can be coupled onto the node with adverse effects. This noize can come in several forms; RF signal noize, transient switching noize, and harmful fault currents on the bus. This block addresses these three forms of noize. The previous node design used a CAN bus, and a Physical Layer (PHY) chip to isolate the electrical connection between the CAN bus, and the microcontroller used at that time. The PHY converted the single ended uni-directional TTL signals from the microcontroller into the differential bi-directional signal pair needed by the CAN bus. This PHY also provided electrical transient suppression, and bus protocol validity logic that prevented and errant microcontroller from disrupting the entire CAN bus for the other bus peers. This is mentioned here because this level of functionality is still desired, however the situation is totally different in the following ways. It should be stated, PHY chips for USB, similar to the one previously used for CAN exist, however are inappropriate for this design. Particularly, the LPC2148 is actually providing the needed differential bi-directional electrical interface needed by USB. A protocol validation logic section is not needed (or would be superflous) since each USB endpoint communicates directly with a USB hub, which essentially provides the function of isolating errant nodes from disrupting the entire bus. Finally the function of electrical transient suppression is provided by this USB filtering block.

The following figure illustrates the USB filtering block.

Fig. Glue.1

Driver impedance matching resistors (R281, R282)

Part Description:

• 33.2 ohm resisior, 1/8 watt, Chip 1% Thick film, 0805 package, Panasonic ERJ-6ENF33R2V, (Digikey P/N P33.2CCT-ND) http://www.panasonic.com/industrial/components/pdf/AOA0000CE2.pdf

Purpose:

• Intrinsic driver impedance R_S, required by USP 2.0 electrical specification.

Specifications/ Calculations:

• The intrinsic driver impedance, R_S, is described in chapter 7.1.1.3 of the USB 2.0 specification, under High Speed Driver Characteristics on page 129. Rs is 1/2 of the total bus impedance of 90 ohms, or 45 ohms. This total value is to include the contributions of cabling, and connectors, and therefor should be less than 45 ohms. See Figure 7-3 in the USB 2.0 spec.

Edge rate control capacitor (C289, C290)

Part Description:

• 18 pF, 50 volt, Chip NP0, 0805 package, Panasonic ECJ-2VB1H103K (Digikey P/N PCC103BNCT-ND) http://www.panasonic.com/industrial/components/pdf/abj0000ce1.pdf

Purpose:

• Edge rate control capacitor, Cedge, intended to obtain the optimal eye pattern of data rise/fall times.

Specifications/ Calculations:

• 7.1.6.1 states this capacitance is to be less than 75 pF, and is to be placed between R_S and the tranceiver. See page 142 of the USB 2.0 specification.

USB Full Speed Select (R291)

Part Description:

• 1.5 k ohm resistor, 1/8 watt, Chip 1% Thick film, 0805 package, Panasonic ERJ-6ENF1501V, (Digikey P/N P1.50KCCT-ND) http://www.panasonic.com/industrial/components/pdf/AOA0000CE2.pdf

Purpose:

• USB Full Speed Select pull-up resistor R_PU, required by USP 2.0 electrical specification to select Full Speed.

Specifications/ Calculations:

• This 1.5 K ohm resistor called R_PU, is to pull-up the D+ signal to 3.3 volt IO power source to indicate Full Speed mode prior to enumeration. It is described in chapter 7, under signaling on page 121 of the USB 2.0 specification.

USB Port Transient Suppressor (U282)

Part Description:

• USB port transient suppressor, Package SOT-23-6, TI SN65220DBVR, (Digikey P/N 296-9694-1-ND) http://focus.ti.com/lit/ds/symlink/sn65220.pdf

Purpose:

• To provide transient voltage suppression that may be picked up on the external USB bus.

Specifications/ Calculations:

• This component provides 15 kV of ESD capability to the D+ and D- USB signals. The part adds 35 pF of capacitance on each signal circuit to ground. This values is still within the USB 2.0 edge capacitance spec of 75 pF. Figure Glue.2 illustrates the parts internal circuit. Figure Glue.3 illustrates the relationship between circuit voltage, and the suppressing current capability.

Image from TI SN65220 datasheet

Fig. Glue.2

Image from TI SN65220 datasheet

Fig. Glue.3

EMI/RF Filter (L281, L282)

Part Description:

• Chip EMI Filter Type EXCCET, Package C type, Panasonic EXC-CET471U, (Digikey P/N P9829CT-ND) http://www.panasonic.com/industrial/components/pdf/AEH0000CE3.pdf

Purpose:

• To suppress RF signals that may be picked up on the external USB bus and still pass the baseband USB signal.

Specifications/ Calculations:

• This component provides RF attenuation on the USB circuit as shown in Figure Glue.4. The baseband USB signal is 12 Mb/sec, giving a worst case frequency (alternating 1010... pattern) of 6 MHz. In order to to attenuate this signal, the device number 471 in Figur Glue.4 should be chosen. This gives a maximum attenuation of about 38 dB at approximately 150 MHz. This maximum attenuation frequency is useful in another respect since we use 146 MHz VHF communications for another avionics subsystem. Note 6 in the data sheet mentions the device deteriorates when subjected to surges or abnormal voltages, therefore it should be placed behind the USB TVSS. The circuit is effectively a Tee fiter, with the shunting member connected to IO ground. Interesting note: The USB 2.0 spec on the bottom of page 142 states that the use of ferrite beads on a full speed USB device is discouraged.

Image from Panasonic EXCCET data sheet

Fig. Glue.4

IO Power and Ground

Purpose:

• The power and ground needed for this block are identified as IO_3.3V and IO_Ground. They are single point connections to the SPS 3.3V and ground, made directly back at the supply to prevent ground loops and to reduce power disturbance with other node systems.

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Power-on reset

Microcontroller Supervisory Circuit (U283)

Part Description:

• Supervisory Circuit, Package SOT-23-3, Microchip MCP130T-315I/TT, (Digikey P/N MCP130T-315I/TTCT-ND) http://rocky.digikey.com/WebLib/Microchip/Web%20Data/MCP120,130%20Series.pdf

Purpose:

• Provide power-on reset of sufficient time duration. Assert reset to lock the processor if V_DD goes below level allowed by microcontroller.

Specifications/ Calculations:

• The LPC2148 has integral power-up reset functionality that needs to be considered in conjunction with this part. The LPC2148 User Manual section 3.10 describes the reset requirements, and section 3.13 describes the brownout functionality. If enabled, the 2148 can generate a "brown-out" interrupt when V_DD goes below 2.9 volts. Additionally the 2148 will internally assert reset if V_DD goes below 2.6 volts. We want to choose the MCP130 threshold voltage to allow this brown-out interrupt to occur, and could override the low V_DD reset assertion, having this provided by the MCP130 instead. Another constraint to choosing the MCP130 threshold voltage is to allow normal SPS load regulation to offur, and not cause an unwanted reset. Jacob assures in the SPS design that V_DD should never go below 3.0 volts under normal output ripple conditions. Infact he indicates that is V_DD does go below 3.0 volts this is a fault condition and something is wrong, and a reset would be appropriate. Figure Glue.5 shows the allowed duration of a voltage drop-out transient allowed before a reset is generated by the MCP130. Normal operation of the SPS is around V_Trip - V_DD = 0.3 volts, which allows a drop-out transient of about 3 us. This is well within the SPS spec according to Jacob. A final constraint is the length of time reset is asserted after power-up. Figure Glue.6 illustrates this relationship, with t_RPU being approximately 275 ms for the MCP130 variant chosen. The LPC User Manual section 3.10 indicates this needs to be at least 10 ms for the first reset as power is first applied, and can be as little as 300 ns for subsequent resets after to chips oscillator is up and running.

Image from Microchip MCP130 datasheet

Fig. Glue.5

Image from Microchip MCP130 datasheet

Fig. Glue.6

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Oscillator and divider

• The crystal based system oscillator is described in the Philips User Manual in chapter 3. This oscillator and divider block provides two functions to the node. First it is the primary system clock for the LPC2148 microcontroller, and second it is a synchronizing oscillator for the SPS. The oscillator amplifier is internal to the LPC2148 with output appearing on X2 (pin 61), and input on X1 (pin 62). The microcontroller internally uses the output of the amplifier to operate it's logic clock circuits. Fig. Glue.7 shows the schematic of this functioal block

Fig. Glue.7

Frequency control crystal (X281)

Part Description:

• 12 MHz Surface Mount Crystal, Fundamental Mode, CS10 package (6.0 mm x 3.3 mm), Citizen CS10-12.0000MABJTR (Digikey P/N 300-8089-1-ND) http://dkc3.digikey.com/PDF/T062/0941.pdf

Purpose:

• The system clock is driven by an internal oscillator amplifier, using an external crystal for frequency reference. This crystal is the primary frequency determining component of the oscillator. The resonant circuit formed by this crystal is in the feedforward path of the oscillator. The oscillator can operate anywhere between 1 and 30 MHz when using this internal amplifier.

Specifications/ Calculations:

• We want the system clock oscillator to produce a frequency that is simultaneously a factor of the highest CPU clock frequency possible (which is 60 MHz), a factor of 48 MHz for the USB clock, and a factor of a frequency somewhere around 1.1 to 1.5 MHz for the SPS synchronization. A 12 MHz system clock meets this need.

  For USB clock: 12 MHz * 4 = 48 MHz For CPU clock: 12 MHz * 5 = 60 MHz For SPS Sync: 12 MHz / 8 = 1.5 MHz

• Specifications required by Phillips in the users manual, table 7 on page 19. Philips provides three posible C_L values. The one closest to the Citizen CS10 is 20 pF.

Oscillator load capacitors (C281, C282)

C281

Part Description:

• 39 pF, 50V, Ceramic chip NP0, 0805, Panasonic ECJ-2VC1H390J, (Digikey P/N PCC390CGCT-ND) http://www.panasonic.com/industrial/components/pdf/abj0000ce1.pdf

Purpose:

• Oscillator load capacitor C_X1. Influences oscillator frequency by being part of the resonant feed forward impedance.

Specifications/ Calculations:

• Specified by Phillips in users manual table 280 on page 286. When choosing a crystal having a C_L of 20 pF, The table specifies C_X1 to be 38 pF. The closest standard value to this is 39 pF.

C282

Part Description:

• 33 pF, 50V, Ceramic chip NP0, 0805, Panasonic ECJ-2VC1H330J, (Digikey P/N PCC330CGCT-ND) http://www.panasonic.com/industrial/components/pdf/abj0000ce1.pdf

Purpose:

• Oscillator load capacitor C_X2. Influences oscillator frequency by being part of the resonant feed forward impedance.

Specifications/ Calculations:

• Specified by Phillips in users manual table 280 on page 286. When choosing a crystal having a C_L of 20 pF, The table specifies C_X2 to be 38 pF. However this capacitor is in parallel with the load capacitance of the CD4024 ripple counter. The nominal load capacitance on all digital inputs of the CD4024 is 5 pF.

  Cl = 38 pF 38 pF = 33pF // 5 pF 33 pF is a standard value

Having the nominal capacitance of C_X1, and C_X2 being slightly unequal provides an increased energy efficiency in the oscillator according to Tim.

Binary ripple counter (U281)

• The 12 MHz clock needs to be divided by 8 to form the 1.5 MHz SPS sync signal. After our research, even today, the smallest package with the most direct approach to providing this divide function is a cascaded series of D flip-flops. One would think there were a better way.

Part Description:

• CD4024 7-stage CMOS ripple counter, 14-TSSOP package, TI CD4024BPWR, (Digikey P/N 296-12760-1-ND) http://focus.ti.com/lit/ds/symlink/cd4020b.pdf

Purpose:

• Divide the 12 MHz clock by 8 to generate a 1.5 MHz SPS sync clock.

Specifications/ Calculations:

• 8 = 2³, so pick off signal at Q3. This divider is also useful for other application specific functions to be identified later since it is simultaneously creating all versions of the system clock divided by 2¹ through 2⁷ inclusively. For convenience I have placed below a diagram which shows the internal configuration of this divider.

Image from TI CD4024 datasheet

Fig. Glue.8

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RTC crystal oscillator

• Chapter 19 in the Philips LPC2148 user manual describes operation of the internal Real Time Clock. The clock keeps time and date in user acessable registers described on page 276 of the user manual. The power for the clock is brought out externally on pin 49, and is seperate from the main power so a battery could power the clock when the CPU is powered off. This will allow the clock time to remain current. It is intended this power be provided by an external 3.2 volt lithium coin cell, and so pins have been brought out to the user-specified area for this. It is also possible to connect the clock power to the main 3.3 volt supply rail if a battery is not available.

Oscillator load capacitors (C283, C284)

C283

C284

Part Description:

• 22 pF, 50V, Ceramic chip NP0, 0805, Panasonic ECJ-2VC1H220J, (Digikey P/N PCC220CNCT-ND) http://www.panasonic.com/industrial/components/pdf/abj0000ce1.pdf

Purpose:

• Oscillator load capacitors, Cx1 and Cx2. Influences oscillator frequency by being part of the resonant feed forward impedance.

Specifications/ Calculations:

• Specified by Phillips in users manual table 280 on page 286.

Frequency control crystal (X282)

Part Description:

• 32.768 kHz Surface Mount Crystal Tuning Fork, CM415 package (4.1 mm x 1.5 mm), Citizen CM415-32.768KDZFTR (Digikey P/N 300-8193-1-ND) http://dkc3.digikey.com/PDF/T062/0942.pdf

Purpose:

• The real time clock is driven by an internal oscillator, using an external crystal for frequency reference. This crystal is the primary frequency determining component of the real time clock oscillator. The resonant circuit formed by this crystal and the two load capacitors is in the feed forward path of the oscillator. The oscillator is intended to operate at 32.768 kHz which is 2¹⁵.

Specifications/ Calculations:

• Specifications required by Phillips are in the users manual, table 280 on page 286.

Power to oscillator

• The RTC has a seperate power source on pin 49 (VBAT). This can be connected to an external 3.2 volt battery, or the SPS 3.3 V supply.

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Debug port

Connector (CM201)

Part Description:

• 16 pin right angle connector, JST-16PS-JED, (Available from JST) http://www.jst.co.uk

Purpose:

• Provide interconnection between the JTAG and UART ports, to the outside world. The UART access allows in-circuit programming of the flash memory. Chapter 21 of the LPC2148 User Manual describes programming. Also see section 6.2.2. ISP Software of this report.

Specifications/ Calculations:

• Small, small, small. Right angle. Something we trust regarding pin integrity. 2006/07/05 TAB and ADG are now thinking 0.5mm pitch LCD style board-to-board connector. Typical: Hirose DF17A(4.0)-40DP-0.5V(57) from Digikey. Using the high density LCD connector, we double up the pins by going straight through the part connecting one side to the other. with 0.5 mm parts, we take every other one on the other side of the connector and via it to the bottom, so from a 30 pin part we get 15 connections, 8 on top and 7 on the bottom (from the far side, via vias).

Pull up/down resistors (R283, 284, 285, 286, 287, 288)

Part Description:

• 10.0 K ohm resistor, Chip 1% Thick film, 1/8 watt, Package 0805, Panasonic ERJ-6ENF1002V, (Digikey P/N P10.0KCCT-ND) http://www.panasonic.com/industrial/components/pdf/AOA0000CE2.pdf

Purpose:

• Pull up/down resistors on JTAG port. Not sure yet of the purpose; suspect to assert a default signal when the port is not connected to a JTAG ICE. This was directly copied from the Olimex Evaluation board's JTAG port.

Specifications/ Calculations:

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Power Good and Shutdown

Power Good

Purpose:

• Input to microcontroller from SPS indicating status of incomming power. Allows the microcontroller to perform evasive action should the power develop a problem.

Specifications/ Calculations:

Power Shutdown

Purpose:

• Output from microcontroller to the SPS to shutdown the SPS. This will allow the SPS to be shut down under software control. If the power comming to the node is still good, the SPS will restart after a predetermined amount of time.

Specifications/ Calculations:

• Assure the default state of this output pin is such to allow the SPS to start before the microcontroller is up and running.

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Breakout of signals to application specific area

Purpose:

• These are the golden resources we are providing to the future application specific functions of this board. Here we have access to all of the unused pins of the microcontroller, and the debug port. There are also unused pins on the debug port that are passed on to the group of connections to allow external access to the application specific area through the debug port.

Specifications/ Calculations:

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Status LEDs

Red LED (D281)

Part Description:

• LED High efficiency red with diffuse lens, Package SOT-23, (Digikey P/N L71516CT-ND) http://dkc3.digikey.com/PDF/T062/1848.pdf

Purpose:

• To provide a user defined status indicator. Controlled by microcontroller.

Specifications/ Calculations:

• Connected to general purpose output pin P1.17; Called Status 2.

Green LED (D282)

Part Description:

• LED Green with clear lens, Package SOT-23, (Digikey P/N L71508CT-ND) http://dkc3.digikey.com/PDF/T062/1848.pdf

Purpose:

• To provide a user defined status indicator. Controlled by microcontroller.

Specifications/ Calculations: Connected to general purpose output pin P1.16; Called Status 1.

Current limit resistors (R289, R290)

R289

R290

Part Description:

• 604 ohm resistor, Chip 1% Thick film, 1/8 watt, Package 0805, Panasonic ERJ-6ENF6040V, (Digikey P/N P604CCT-ND) http://www.panasonic.com/industrial/components/pdf/AOA0000CE2.pdf

Purpose:

• LED current limit resistor.

Specifications/ Calculations:

• V_f = 2.1 V. We specified the LED drive current to be 2 mA.

  3.3V - 2.1V = 1.2V 1.2V / 2 mA = 600 ohm Closest standard value is 604 ohm

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Test points

SPS Off

Pwr Good

1.5 MHz (SPS Sync)

Purpose:

• To gain access to signals during testing.

Specifications/ Calculations:

• These are just small scrape pads on the PCB to touch a test probe onto.

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Configuration trace-cuts or solder jumpers

Analog V_REF

RTC Power (V_BAT)

Purpose:

• To allow alternate configuration of these supply voltages.

Specifications/ Calculations:

• The default is to use SPS power. To use the alternate source, cut the fine trace between the default pads, and reconnect the alternate with a solder bridge.

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Bill of materials (BOM)

Following are the components needed to construct the Glue section of the board.

• The quantity is the number of individual pieced needed. This number may need to be increased to fit the minimum order size.
• The first three columbs are Digi Key Fast-Add order format fields provided the quantiny is properly adjusted.

NOTES: (1) C285, 286, 287, 288, 291, 292 should be a 100 nF cap, not 10 nF.

"*" Needs to be ordered