PSAS/ capstone2009/ design/ aps/ switches
  1. Requirements:
  2. Chosen Integrated Circuits:
    1. Switch Controller IC (TPS2490)
      1. Controller Datasheet
      2. Initial reasons for choosing TPS2490:
    2. N-Channel MOSFET transistor (Si4122DY)
      1. FET Datasheet
  3. Power Switch Design
    1. TPS2490 Pin Descriptions:
      1. VCC
      2. SENSE
      3. GATE
      4. OUT
      5. EN
      6. VREF
      7. PROG
      8. TIMER
      9. PG
      10. GND
    2. TPS2490 Functional Descriptions:
      1. APS Power Switch Basic Functional Description
      2. Under Voltage Lockout (UVLO)
      3. Constant Power Engine
      4. TIMER Operation
      5. Soft-Start
      6. dV/dt Control
    3. APS Power-Switch Component Selection
      1. Integrated Circuits:
        1. U2000 - U2007
      2. Transistors:
        1. Q2000 - Q2007
      3. Connectors:
        1. J2000 - J2007
      4. LEDs:
        1. LED2000 - LED2007
      5. Resistors:
        1. R2000 - R2007
        2. R2008 - R2015
        3. R2016 - R2023
        4. R2024 - R2031
        5. R2032 - R2039
        6. R2040 - R2047
        7. R2048 - R2055
        8. R2056 - R2063
      6. Capacitors:
        1. C2000 - C2007
        2. C2008 - C2015
        3. C2016 - C2023
        4. C2024 - C2031
        5. C2032, C2033
        6. C2044 - C2051


The specifications the APS power switches are required to meet are as follows:

Chosen Integrated Circuits:

Switch Controller IC (TPS2490)

Controller Datasheet

TPS2490 datasheet

Initial reasons for choosing TPS2490:

N-Channel MOSFET transistor (Si4122DY)

FET Datasheet

Si4122DY datasheet

Power Switch Design

TPS2490 Pin Descriptions:


This pin serves 3 functions (See Function Descriptions for explanations of specific functions):

  1. biasing power to the controller IC
  2. Input to power on reset (POR) and under voltage lockout functions (UVLO)
  3. Voltage sense at one of the terminals of sense resistor Rs (See Typical Application diagram on page 1 of datasheet)


Connects to downstream terminal of sense resistor Rs. This pin monitors the voltage at the FET drain (refered to as M1 in datasheet) and Rs terminal to provide feedback to the controller's constant power limiting engine (see Function Descriptions) as to M1 current (Id) and voltage (Vds). Id is calculated using voltage difference between VCC and SENSE pins divided by the value of sense resistor Rs. Vds is calculated with the difference between voltages on SENSE and OUT pins.


Provides the high side gate drive for the FET M1. This pin is controlled by the internal gate drive amplifier which provides a pullup of 22uA from an internal charge pump and a strong pulldown to ground of 75mA. Pull-down current is a non-linear function of the amplifier overdrive providing small overdrive for small overloads, and large overdrive fro fast reaction to output shorts. This pin also employs a seperate 2mA pull-down to shut off transistor M1 when voltage on EN pin, or UVLO conditions cause this to happen.


This pin is used by the constant power engine and PG comparator to measure Vds of M1 transistor. Internal protection circuits leak a small current from this pin when it is low.


The TPS2490 gate drive is enabled if the positive threshold is exceeded and internal POR and UVLO thresholds have been satisfied. If the IC is latched off, it can be reset by cycling the EN pin below the negative threshold and then back high. The voltage thresholds for this pin are as follows:


Provides a 4V reference voltage for use in setting the voltage on the PROG pin. This voltage is available once the POR and UVLO thresholds have been satisfied. This pin supplies no more than 1mA of current.


The voltage applied to this pin programs the power limit used by the constant power engine. The voltage on this pin is set using a resistor divider circuit on the VREF pin.


An integrating capacitor, Ct in reference design, connected to this pin provides a timing function that controlls the fault time. The TIMER pin charges the capacitor with a 25uA current whenever the TPS2490 is in power limit or current limit, and discharges at 2.5uA otherwise. If the voltage on the TIMER pin reaches 4V, the controller pulls the gate to ground, latches off, and discharges capacitor Ct.


This open-drain output is intended to interface to downstream dc/dc converters or monitoring circuits. PG pin goes open drain (high-voltage with pull-up) after Vds of FET M1 has fallen to about 1.25V and a 9ms deglitch time has passed. PG is false (low) when EN is false, Vds is above 2.5V, or UVLO is active.


This pin is connected to system ground

TPS2490 Functional Descriptions:

APS Power Switch Basic Functional Description

The power switch network employed on the LV2c APS node consists of 7 power switches which provide overcurrent protection for 7 downstream devices. An 8th switch is also employed which provides the same protection for the upstream flight computer. Under normal operation the external N-Channel MOSFET is turned on via the TPS2490 gate drive and power is supplied to peripheral devices through a 16 pin connector. The remaining pins on the connector are used for differential USB and CAN data signals as well as auxilliary pins for direct board to board connections. Each switch is designed for a maximum current limit of 5A along with an allowable 100% (10A) inrush limit which the switch will allow for 100ms without fault to the attached device. Each switch uses a logic enable which is connected to the ARM micro-controller to give full control over which devices are powered. The PG (power good) pin of each switch is also connected to the ARM to indicate the on/off status of each switch.

Under Voltage Lockout (UVLO)

This function will disable the switches in the event of a hard short on the main power path. The switches will latch off if the voltage on VCC reaches or falls below 8.3V.

Constant Power Engine

This function monitors the power dissipation in the external MOSFET for the main purpose of limiting rise in the junction temperature of the FET. Thermal ratings of the FET are used to determine the value of maximum power dissipation allowable. From the datasheet description, this function generally applies to startup conditions as this is when the FET will experience inrush over-currents and run the risk of exceeding its physical limitations. This, in turn, can result in not only damage or destruction of the FET, but damage or destruction of the attached device as well. The constant power engine varies the transistor current, Id, as the voltage, Vds, changes in order to ensure that power dissipation remains constant at the programmed value. As stated, the actual power limit value is determined using thermal parameters of the FET used in the design in the following equation:

Plim <= 0.7 x (Tjmax2 - [(I^2max x Rdson x Rthca) + Tamax])/Rthjc


Using the above equation and the given values:

Plim <= 1.755W

This value can then be programmed into the TPS2490 by applying the voltage to PROG pin which satisfies the following equation given in the datasheet:

VPROG = Plim/(10xIlim)

This equation is derived from the fact that the constant power engine has an output clamped to 50mV according to:


Solving for VPROG:

VPROG = 0.05V x [2x(VSENSE-VOUT)] = 0.1 x (VSENSE - VOUT)

Since Plim = Ilim x Vds = Ilim x (VSENSE - VOUT):

VPROG = [0.1 x Ilim x (VSENSE - VOUT)]/Ilim = Plim/(10xIlim)

The calculated VPROG is applied to the PROG pin using a resistor divider circuit in conjunction with VREF. See conponent selection for resistor values and calculations.

At startup we can assume that Vds = VCC. The initial current through the FET, Id-allowed, is then determined by the set power limit according to:

Id-allowed = Plim/VCC

After stepping to this initial value of Id-allowed, Vds falls and Id is allowed to increase in such a way as to ensure that Plim remains constant. This happens because the power limiting engine adjusts the current limit reference to the gate amplifier thus controlling the transition of the FET from off to fully on, and allowing the transients to pass before it reaches the fully-on state. In non-startup overcurrent conditions, power limiting is assumed to be achieved in a similar fashion. In this situation the volatge at VSENSE will increase due to the rise in current through sense resistor Rs and Id-allowed will be adjusted to ensure that the power dissipation remains constant according to the set limit.

TIMER Operation

In the event that the power limiting engine is activated, a 25uA current is supplied be the TIMER pin to charge the capacitor Ct. Once the capacitor's charge reaches 4V, the FET is turned off and the TPS2490 latches off. The switch then must be reset by cycling the EN pin. See C2000 - C2007 in the component selection for calculation of the capacitor values.


In the description of the constant power limiting engine, it is mentioned that at startup there is a small stepup in Id-allowed to satisfy the power limiting engine. This initial step up in current could pose a potential problem depending on its magnitude. As such, the switch can be designed with a capacitor added to the PROG pin to employ a soft-start function which converts this step into a ramp. The value of the capacitor would then determine the slope of teh ramp. See C2008-C2015 in component selection for more info.

dV/dt Control

The TPS2490 provides the option of dV/dt control in applications which require constant turn on currents for the FET. This is achieved through the addition of a resistor in series with a capacitor connected from the GATE pin to ground. See C2016-C2023 and R2048-R2055 in component selection.

APS Power-Switch Component Selection

Integrated Circuits:

U2000 - U2007


Q2000 - Q2007


J2000 - J2007


LED2000 - LED2007


R2000 - R2007

R = 0.05V/(1.2 x 5) = 8.33mOhm

R2008 - R2015

R2016 - R2023

R2024 - R2031

Vprog = Plim/(10 x Ilim,max) = 1.755/(10 x (1.2x5)) = 0.02925V

Vprog = Vref(R/(10k + R))

R = 73.664Ohm

R2032 - R2039

R2040 - R2047

R2048 - R2055

R2056 - R2063


C2000 - C2007

I = C(dV/dt)

I = 25uA

dV/dt = 4V/100ms

C = I/(dV/dt) = 25uA/(4V/100ms) = 0.625uF

C2008 - C2015

C2016 - C2023

C2024 - C2031

C2032, C2033

C2044 - C2051