- Chosen Integrated Circuits:
- Power Switch Design
- TPS2490 Pin Descriptions:
- TPS2490 Functional Descriptions:
- APS Power-Switch Component Selection
- Integrated Circuits:
The specifications the APS power switches are required to meet are as follows:
- Power Switches
- MUST have (8,,) independent resettable electronic circuit breakers with adjustable current trip and trip delay. Setting can be via resistor strap, EEPROM, etc. Current trip should be latch-off or selectable.
- MUST have Soft on/off feature
- MUST have no mechanical switches in main power path.
- MUST indicate power switch on/off state (LED for human, and electrical signal for APS node)
- MAY indicate power switch fault state
- MUST operate continuously within 20% of the over-current set point
- MUST allow set currents in the range (0.1, 5)A
- MUST allow over current transients of 100% for minimum 100 ms without fault to the load
The design of the APS power switches will be similar to those used in the LV2b APS in that they will each consist of an external FET combined with a controller IC. This is mainly because of the fact that this form of switch is very robust and reliable and still offers a great deal of control over the various parameters in order to meet the specs. Aside from the ability to meet above specs, some major considerations when choosing components were:
Larger supply voltage (designing for 20V or greater, max for old controller was 18V)
- High side switch (reacts to fault at high rather than low side of switch)
- Require FET which has a low Rds-on which is ideal in that we want the FET to resemble a wire as closely as possible when on
- Simpler design requiring less external components
- The IC chosen as the controller is the TPS2490 Postitive High-Voltge Power-Limiting Hotswap Controller by Texas Instruments. Click below to view this item's datasheet.
- Wide operating voltage (+9V to +80)
- Under voltage lockout feature
- Simpler reference design than LTC1154 (used on LV2b APS)
- MSOP package
- Programmable fault timer
- Programmable power limit to limit dissipation in FET
- The transistor choice was based on a large Vds range, small Rds-on, and relatively small package size. The FET chosen is the Vishay Si4122DY N-channel MOSFET which is rated at a max Vds of 40V and and Rds-on of 4.5mOhm at a Vgs of 10V.
- The following pin descriptions were taken from the datasheet. For a more in depth description, see pages 9 and 10.
This pin serves 3 functions (See Function Descriptions for explanations of specific functions):
- biasing power to the controller IC
- Input to power on reset (POR) and under voltage lockout functions (UVLO)
- Voltage sense at one of the terminals of sense resistor Rs (See Typical Application diagram on page 1 of datasheet)
Connects to downstream terminal of sense resistor Rs. This pin monitors the voltage at the FET drain (refered to as M1 in datasheet) and Rs terminal to provide feedback to the controller's constant power limiting engine (see Function Descriptions) as to M1 current (Id) and voltage (Vds). Id is calculated using voltage difference between VCC and SENSE pins divided by the value of sense resistor Rs. Vds is calculated with the difference between voltages on SENSE and OUT pins.
Provides the high side gate drive for the FET M1. This pin is controlled by the internal gate drive amplifier which provides a pullup of 22uA from an internal charge pump and a strong pulldown to ground of 75mA. Pull-down current is a non-linear function of the amplifier overdrive providing small overdrive for small overloads, and large overdrive fro fast reaction to output shorts. This pin also employs a seperate 2mA pull-down to shut off transistor M1 when voltage on EN pin, or UVLO conditions cause this to happen.
This pin is used by the constant power engine and PG comparator to measure Vds of M1 transistor. Internal protection circuits leak a small current from this pin when it is low.
The TPS2490 gate drive is enabled if the positive threshold is exceeded and internal POR and UVLO thresholds have been satisfied. If the IC is latched off, it can be reset by cycling the EN pin below the negative threshold and then back high. The voltage thresholds for this pin are as follows:
- V-EN-High: typical 1.35V
- V-EN-Low: typical 1.25V
Provides a 4V reference voltage for use in setting the voltage on the PROG pin. This voltage is available once the POR and UVLO thresholds have been satisfied. This pin supplies no more than 1mA of current.
The voltage applied to this pin programs the power limit used by the constant power engine. The voltage on this pin is set using a resistor divider circuit on the VREF pin.
An integrating capacitor, Ct in reference design, connected to this pin provides a timing function that controlls the fault time. The TIMER pin charges the capacitor with a 25uA current whenever the TPS2490 is in power limit or current limit, and discharges at 2.5uA otherwise. If the voltage on the TIMER pin reaches 4V, the controller pulls the gate to ground, latches off, and discharges capacitor Ct.
This open-drain output is intended to interface to downstream dc/dc converters or monitoring circuits. PG pin goes open drain (high-voltage with pull-up) after Vds of FET M1 has fallen to about 1.25V and a 9ms deglitch time has passed. PG is false (low) when EN is false, Vds is above 2.5V, or UVLO is active.
This pin is connected to system ground
The power switch network employed on the LV2c APS node consists of 7 power switches which provide overcurrent protection for 7 downstream devices. An 8th switch is also employed which provides the same protection for the upstream flight computer. Under normal operation the external N-Channel MOSFET is turned on via the TPS2490 gate drive and power is supplied to peripheral devices through a 16 pin connector. The remaining pins on the connector are used for differential USB and CAN data signals as well as auxilliary pins for direct board to board connections. Each switch is designed for a maximum current limit of 5A along with an allowable 100% (10A) inrush limit which the switch will allow for 100ms without fault to the attached device. Each switch uses a logic enable which is connected to the ARM micro-controller to give full control over which devices are powered. The PG (power good) pin of each switch is also connected to the ARM to indicate the on/off status of each switch.
This function will disable the switches in the event of a hard short on the main power path. The switches will latch off if the voltage on VCC reaches or falls below 8.3V.
This function monitors the power dissipation in the external MOSFET for the main purpose of limiting rise in the junction temperature of the FET. Thermal ratings of the FET are used to determine the value of maximum power dissipation allowable. From the datasheet description, this function generally applies to startup conditions as this is when the FET will experience inrush over-currents and run the risk of exceeding its physical limitations. This, in turn, can result in not only damage or destruction of the FET, but damage or destruction of the attached device as well. The constant power engine varies the transistor current, Id, as the voltage, Vds, changes in order to ensure that power dissipation remains constant at the programmed value. As stated, the actual power limit value is determined using thermal parameters of the FET used in the design in the following equation:
Plim <= 0.7 x (Tjmax2 - [(I^2max x Rdson x Rthca) + Tamax])/Rthjc
- Rthjc = FET junction to case thermal resistance (42 degC/W)
- Tjmax2 = short term max die temp. of FET, can be set at 150C if max rating is 175C, since Si4122DY max is 150C, we'll set this to 150C - 25C = 125C
- Rdson is the FET ds on resistance at max operating temp. of about 80C. This value is 4.5mOhm
- 0.7 represents the tolerance of the constant power engine
- Rthca = the max case to ambient thermal resistance; equal to Rthja - Rthjc = 21degC/W
- I^2max = the square of the max drain current, Id, allowed (5A) = 25
- Tamax = maximum ambient temperature (assuming around 70C)
Using the above equation and the given values:
Plim <= 1.755W
This value can then be programmed into the TPS2490 by applying the voltage to PROG pin which satisfies the following equation given in the datasheet:
VPROG = Plim/(10xIlim)
This equation is derived from the fact that the constant power engine has an output clamped to 50mV according to:
VPROG/[2x(VSENSE-VOUT)] = 50mV
Solving for VPROG:
VPROG = 0.05V x [2x(VSENSE-VOUT)] = 0.1 x (VSENSE - VOUT)
Since Plim = Ilim x Vds = Ilim x (VSENSE - VOUT):
VPROG = [0.1 x Ilim x (VSENSE - VOUT)]/Ilim = Plim/(10xIlim)
The calculated VPROG is applied to the PROG pin using a resistor divider circuit in conjunction with VREF. See conponent selection for resistor values and calculations.
At startup we can assume that Vds = VCC. The initial current through the FET, Id-allowed, is then determined by the set power limit according to:
Id-allowed = Plim/VCC
After stepping to this initial value of Id-allowed, Vds falls and Id is allowed to increase in such a way as to ensure that Plim remains constant. This happens because the power limiting engine adjusts the current limit reference to the gate amplifier thus controlling the transition of the FET from off to fully on, and allowing the transients to pass before it reaches the fully-on state. In non-startup overcurrent conditions, power limiting is assumed to be achieved in a similar fashion. In this situation the volatge at VSENSE will increase due to the rise in current through sense resistor Rs and Id-allowed will be adjusted to ensure that the power dissipation remains constant according to the set limit.
In the event that the power limiting engine is activated, a 25uA current is supplied be the TIMER pin to charge the capacitor Ct. Once the capacitor's charge reaches 4V, the FET is turned off and the TPS2490 latches off. The switch then must be reset by cycling the EN pin. See C2000 - C2007 in the component selection for calculation of the capacitor values.
In the description of the constant power limiting engine, it is mentioned that at startup there is a small stepup in Id-allowed to satisfy the power limiting engine. This initial step up in current could pose a potential problem depending on its magnitude. As such, the switch can be designed with a capacitor added to the PROG pin to employ a soft-start function which converts this step into a ramp. The value of the capacitor would then determine the slope of teh ramp. See C2008-C2015 in component selection for more info.
The TPS2490 provides the option of dV/dt control in applications which require constant turn on currents for the FET. This is achieved through the addition of a resistor in series with a capacitor connected from the GATE pin to ground. See C2016-C2023 and R2048-R2055 in component selection.
- Texas Instruments TPS2490 Positive High-Voltage Power-Limiting Hotswap Controller
- This IC acts as the controller which determines whether or not the external FET is on/off based on several parameters. See above for in depth description of IC functions
- Vishay Si4122DY N-Channel MOSFET
- These transistors are used in conjunction with the TPS2490 as described above
- Modified JST-16PS-JED 16-pin Connector.
- These connectors are used to connect the 7 downstream devices and Flight-Computer to the power switches. The connectors are modified in that they have added "blocks" which allow the plugs from the external devices to be screwed into place, similar to the connection between monitor and computer of a desktop unit
- The pins of each connector are doubled up for redundancy and pin descriptions for each connector are as follows:
- 2 pins - positive battery power/shore power, connected to the output of the FET on each switch
- 2 pins - battery ground/shore ground
- 2 pins - CAN-H; high level of differential CAN data signal
- 2 pins - CAN-L; low level of differential CAN data signal
- 2 pins - USB-H; high level of differential USB data signal
- 2 pins - USB-L; low level of differential USB data signal
- 2 pins - AUX-1; available for optional board to board connections
- 2 pins - AUX-2; available for optional board to board connections
- Green LEDs, 0805 package, used to indicate on/off state of the power switches
These resistors are the sense resistors (Rs as refered to in datasheet) used to set the current limit, Ilim, allowed through the FET
VCC and SENSE pins are connected to the terminals of these resistors and the TPS2490 computes the voltage VCC - VSENSE. This voltage drop is compared internally to a 50mV threshold voltage via an internal comparator. If the voltage exceeds the 50mV threshold, an overcurrent condition exists and the TPS2490 begins limiting action.
The value of these resistors is calculated as follows:
R = 0.05V/(1.2 x Ilim)
Where the factor of 1.2 ensures a 20% operating current tolerance
With Ilim = 5A:
R = 0.05V/(1.2 x 5) = 8.33mOhm
- Gate resistors used to minimize noize on the gate drive of each switch
- It is recommended in the TPS2490 datasheet that if Ciss of the MOSFET > 200pF, a 10 Ohm resistor should be used, otherwise this should be 33Ohm
- Ciss of the Si4122DY = 4200pF so these resistors will be 10 Ohm
- The top resistor in the resistor divider circuit used in conjuction with the 4V reference voltage at VREF to set the voltage on the PROG pin and thus program the power limit for the constant power engine.
- Datasheet notes this resistor can be 4kOhm or greater but it is recommended that 10kOhm or greater be used so these resistors will be 10kOhm
- The bottom resistor for the voltage divider circuit used in conjunction with the 4V reference voltage ate VREF to set the voltage on the PROG pin and program the power limit for the constant power engine
- With the power limit, Plim, already calculated to be 1.755W (see constant power limit engine description) the voltage needed at PROG pin can be calculated:
Vprog = Plim/(10 x Ilim,max) = 1.755/(10 x (1.2x5)) = 0.02925V
- With the top resistor value set at 10kOhm, the value of these resistors can be calculated by solving the following equation for R:
Vprog = Vref(R/(10k + R))
- Solving for R we obtain:
R = 73.664Ohm
- If we set these resistors at 75Ohm, Vprog becomes 0.02977V making Plim 1.79W which is an increase of only about 0.04W and doesn't seem as though it would present a problem
- 10kOhm pull down resistors for the logic enable function of TPS2490
- In the event that the micro-controller malfunctions or for some reason does not turn on the TPS2490, this pull down ensures that the switch will be latched off
- 10kOhm pullup resistors for the power good (PG) pin.
- Since PG is open - drain when 'true', the pullup ensures that PG goes high after Vds falls below 1.25V and a 9ms deglitch time has elapsed
- These resistors are place holders in case the dV/dt control function is needed. At this point they are not placed
- These resistors are current limit resistors to ensure LEDs don't burn up during operation.
- 5kOhm seems to be a reasonable value
- Timeout capacitors connected to the TIMER pin of the TPS2490 (Ct in the datasheet)
- These capacitors control the amount of time a fault is allowed before latch off
- The spec calls for a 100ms time delay
- It is given that during a fault, this capacitor is charged to 4V with a 25uA current before latch-off occurs, thus we can solve for the capacitor values as follows:
I = C(dV/dt)
I = 25uA
dV/dt = 4V/100ms
C = I/(dV/dt) = 25uA/(4V/100ms) = 0.625uF
- These capacitors are placeholders in case the soft start function is required (see function descriptions above)
- In this design, soft-start is not used so these capacitors are not placed
- These capacitors are placeholders in the case that the optional dV/dt function is needed (see function description above)
- In this design we are not using the dV/dt function so these capacitors are not placed
- 0.1uF bypass capacitors which act to eliminate high frequency glitches on VCC pin of TPS2490
- 0.1uF bypass capacitors to eliminate high frequency glitches between main power and main ground
- 0.1uF ESD protection capacitors for the 16 pin connectors