wiki/ CanDeviceBusTimings

Can Controller Device Bus Timings

On the Flight Computer board, we use an Intel 82527 chip. It is running off an 8 MHz clock line (SCLK= 8 x 106). The period of time for one clock cycle is called a time quantum (tq). The way we have the chip configured, a bit time is 8 time quanta long, reuslting in a bit rate of 1 MHz. One bit time looks like this:

                 clock cycle number
        0   1   2   3   4   5   6   7   8
        |   |               |           |
        sync|<--- tseg1 --->|<- tseg2 ->|

The i82527 expects to see an edge transition during the single "sync" time quantum. Then, it allows tseg1 to elapse. It samples the data line at that instant, then allows tseg2 to elapse.

Actually, tseg1 or tseg2 may be shortened or lengthened by the hardware (automatically) as much as 1 clock cycle if it detects a need to resynchronize (this is controlled by the tsjw parameter).

The number of time quanta for tseg1, tseg2, and tsjw can be configured by twiddling the Bit Timing Register 0 (address 0x3f) and Bit Timing Register 1 (address 0x4f).

        bit timing register 0
        |  SJW  |         BRP           |

The tsjw is caculated as 1 time quantum for an SJW value of 0, 2 time quanta for SJW value of 1, etc. We set SJW to zero.

The BRP is used to identify the length of a time quantum, tq. tq = (BRP + 1) / SCLK. Since we want to run at the full rate, we set BRP to zero.

        bit timing register 1
        |Spl|  TSEG2    |    TSEG1      |

Spl is used to cause the I82527 to sample the bus three times in one time quantum and report the majority winner. We leave it zero.

The tseg1 is caclulated as 1 time quantum for a TSEG1 value of 0, 2 time quanta for a TSEG1 value of 1, etc. We use a value of 3.

The tseg2 is calculated as 1 time quantum for a TSEG2 value of 0, 2 time quanta for a TSEG2 value of 1, etc. We use a value of 2.

There are some restrictions on the various parameters. Please refer to the 27241003.pdf document (Intel 82527 Serial Communications Controller Architectural Overview)

-- ?JamesPerkins - 14 Apr 2002