Things to Look for

* fast flash

the process type (e.g. 0.1u process)
power consumption
Serial boot (also known as UART boot, ROM boot, and boot loader)
wait states on the memory (1 wait state means you lose one clock cycle)
PLL
real time clock
has eCos been ported to it?
drivers
software tools support (and what license is it under)
internal interrupt handling
clock generation - how many PLLs will we use
internal voltage regulators - we want to avoid them
memory read speeds and widths
ADC speed - need at least 2.5KHz on each channel (not total)
pin tradeoffs - what do we need and what do we have to give up to get it?
how long to bring up internal oscillators?
5V tolerance on GPIO

Datasheets

Notes

Flash

30MHz worst case. Page programming 6ms, 3ms with auto-erase; full chip erase 15ms.

Power Consumption

90mW max (10mA * 3.3V = 33mW; 50mA * 1.8V = 90mW).

Serial Boot

Has serial boot and USB boot.

Wait states

Up to 3 programmable wait states. (Why you would want to have *more* waitstates?). Prefetch buffer expects 16-bit requests.

PLL

One PLL, 80MHz to 220MHz output. The full spec mentions a minimum frequency input for the PLL that should not be violated, but it doesn't say what that number is!

RTC

No RTC; instead it has RTT (real-time timer) that counts elapsed seconds.

eCos

eCos was ported to an AT91SAM7S-EK (evaluation kit with an AT91SAM7S64 processor). It has drivers for serial I/O (polled and interrupt), flash, watch dog timer, and SPI. The processor had embedded USB, but there's no drivers for it.

Software and Tools

In-System Programmer (for serial/USB, perhaps?). They have lots of other software, but it's customized for the AT91RM9200 microcontroller.

Clock Generation

Andrew thinks we're forced to run the chip at 48MHz (because they only have a divider for the main clock and we need 48MHz for the USB clock). We may be able to use a 12, 6, or 4MHz oscillator, but we'll probably go with a 4MHz crystal.

Internal Voltage Regulators

There is a 1.8V internal regulator, but it can be overridden (VDDCORE and VDDPLL have external pins we can hook up to either the internal regulator or an external regulator).

USB

Atmel claims endpoint 0 can be control, bulk, or interrupt, but we know endpoint 0 needs to be a control endpoint to the host. They use the term "ping-pong" mode??

Atmel - 4 endpoints, with some flexibility for assigning types.

Num. endpoints	Type	Max Packet Size (bytes)
1	control	8
2	isoc/bulk/interrupt	64
1	control/bulk/interrupt	64

So, we basically have only two isocronous endpoints on the Atmel chip, and we're limited to 64 byte packets.

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