Links:
Here's a link to documentation on the AMD Elan SC520: http://www.amd.com/products/epd/processors/4.32bitcont/14.lan5xxfam/24.lansc520/
Info on the MOPS/520 Intel 82527 CAN Configuration
On power up, with no configuration, the 82527 had the following properties:
- Crystal = 8.0MHz
- CLLKOUT = 4.0MHz
- Address Mode 3: (Mode1 pin = 1, Mode0 pin = 1) selects an 8-bit non-multiplexed ad-
dress data bus for either synchronous or asynchronous communication. The asynchronous mode uses R/W#, CS#, and DSACK0# (E=1). The synchronous mode uses R/W#, CS#, and E.
Clocks on board: XTAL (outboard crystal), SCLK (system ( = CAN statemachine & thus CAN bitrate) clock), MCLK (memory (CPU interface) clock). Because the crystal is 8MHz, we'll stick with the defaults of FXTAL = SCLK = MCLK.
| fXTAL | SCLK (DSC bit) | MCLK (DMC bit) |
| 8 MHz | 8 MHz (0) | 8 MHz (0) |
Configuration registers
Control Register @ 0x00
| Mode | Rsvd | CCE | Rsvd | EIE | SIE | IE | Init |
| Configure (off bus) | 0 | 1 | 00 | 0 | 0 | 0 | 1 |
| Run (On bus) | 0 | 0 | 00 | 0 | 1 | 1 | 0 |
CPU Interface Register @ 0x02
| ?RstSt | DSC | DMC | ?PwD | Sleep | Mux | Rsvd | CEn |
| read = 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bit timing on the 82527
We want to run the CAN bus at 1Mbps. This means 1us per bit. The CAN bus defines three time "slices" to each bit (the time it takes to transmit one bit):
| Tsync | Tseg1 | Tseg2 |
Each of these sections are defined in terms of "time quanta" Tq which is based on the 82527's crystal. In our case, with a 8.0MHz crystal, a Tq is 1/8MHz = 125ns. Usually if Tq << Tbit, then you can do this nifty technique of sampling the bit three times and letting the samples vote on what the bit it (0 or 1). This helps with noise. However, in our case Tq ~ Tbit so we'll have to skip the "sampling option" and just take a snapshot of the bit at one time - the border between Tseg1 and Tseg2.
The sections also require certain rules:
| Tsync | Tseg1 | Tseg2 |
| 1 Tq | >= 3Tq | >= 2Tq |
Other constraints are:
- Tseg1 > = Tsjw + Tprop
- Tseg2 > = Tsjw
Where the "synchronization jump width" is how many Tq the 82527 can jump in order to resynchronize bit edges. QUESTION: Does it specify the maximum the chip CAN jump? and the chip jumps less if necessary? Or does it always jump Tsjw?
Given all of this, it makes sense to do:
| Tsync | Tseg1 | Tseg2 | = Total Bit Time |
| 1 Tq | 4Tq | 3Tq | = 8 Tq = 8 * 125ns = 1us = 1MHz |
So, in terms of registers:
Bit Timing Register 0 @ 0x3F
| SJW | BRP |
| 00 (=1Tq) | 000000 (=SCLK) |
Bit Timing Register 1 @ 0x4F
| Spl | TSEG2 | TSEG1 |
| 0 (1 sample only) | 011 (=4Tq) | 0010 (=3Tq) |
Note that the CLKOUT register has to do with providing an external clock for some other chip (like a microcontroller, so we can ignore it). However, to reduce EMI, I'd recommend (ONLY if nothing else uses the clock output, which I doubt they do):
| Reserved | SL1 | SL0 | CDv |
| 00 | 1 | 1 | 1110 |
-- AndrewGreenberg - 22 Aug 2001